Current redundant-execution systems commonly employ a checker circuit that is self-checking and is implemented in hardware. Similar to the checker circuit is the compare instruction that would compare the results from two threads (e.g., store address and data). It may be possible to duplicate the compare instruction in both threads to get the effect of self-checking via duplication.
Unfortunately, by duplicating the compare instruction the architecture would lose the performance advantage of redundant multithreading (RMT). RMT's performance advantage comes from having the leading and trailing threads sufficiently apart such that the leading thread can prefetch cache misses and branch mispredictions for the trailing thread. If the compare instruction is duplicated, not only are additional queues needed, incurring higher overhead, but also the architecture would be unable to keep the two threads sufficiently apart because of the synchronization required in both directions. Thus what is needed is an instruction that can achieve lower failure rate without sacrificing the performance advantage of RMT.